1. Technical Field
The present invention relates generally to power management in processing systems, and more particularly, to a power management scheme that includes an intelligent device controller providing local control of device power management states.
2. Description of the Related Art
Present-day computing systems include sophisticated power-management schemes for a variety of reasons. For portable computers such as “notebook”, “laptop” and other portable units including personal digital assistants (PDAs), the primary power source is battery power. Intelligent power management extends battery life, and therefore the amount of time that a user can operate the system without connecting to a secondary source of power. Power management has also been implemented over “green systems” concerns so that power dissipated within a building is reduced for reasons of energy conservation and heat reduction.
Recently, power management has become a requirement in line power connected systems, particularly high processing power cores and systems because the components and/or systems are now designed with total potential power consumption levels that either exceed power dissipation limits of individual integrated circuits or cabinets, or the total available power supply is not designed to be adequate for operation of all units simultaneously. For example, a processor may be designed with multiple execution units that cannot all operate simultaneously due to either an excessive power dissipation level or a problem in distributing the requisite current level throughout the processor without excessive voltage drop. Or, a memory subsystem may permit installation of more memory than the system power budget/dissipation budget will allow, in order to accommodate large disk/server caches, scientific data arrays and the like without having to include power distribution that can support the maximum installable memory operating at full power, since the entire memory is not generally active at all times and portions of the memory array can be put in a power-savings mode.
However, power management of memory or other system components introduces latency/availability problems in that recovery from a power saving state involves overhead that reduces processing throughput. Further, traditional memory allocation schemes within operating systems tend to exacerbate the problem by spreading frequently accessed memory locations throughout available memory. Memory allocation and processor-managed power management techniques have been proposed and implemented that alleviate this problem to some degree, but fall short of ideal due to the lack of information or latency of information about actual memory use that could otherwise provide for more efficient power management of infrequently used memory that is allocated for a running process. The above-mentioned power management schemes generally activate memory that is in a power saving state if it is used by the process activated at a context switch. Therefore, a seldom-accessed memory module (or bank) that is nonetheless allocated for a process going active will be restored from a power-saving mode at the context switch, even if keeping the memory module in the power-saving mode would only introduce a slight performance hit due to the infrequent access.
It is therefore desirable to provide a method and system for providing power management within a processing system, and in particular within a memory subsystem that can reduce power consumption by placing infrequently used resources in a power-saving state, while providing high processing throughput by maintaining low resource latency for frequently used resources.